one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 pin configuration rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a precision, low cost dual bifet op amp AD642 product description the AD642 is a pair of matched high speed monolithic bifet operational amplifier fabricated with the most advanced bipolar, jfet and laser trimming technologies. the AD642 offers matched bias currents that are significantly lower than currently available monolithic dual fet input operational amplifiers: 35 pa max matched to 25 pa for the AD642k and l; 75 pa max, matched to 35 pa for the AD642j and s. in addition, the offset voltage is laser trimmed to less than 0.5 mv and matched to 0.25 mv for the AD642l, 1.0 mv and matched to 0.5 mv for the AD642k, utilizing analogs laser-wafer trimming (lwt) process. the tight matching and temperature tracking between the operational amplifiers is achieved by ion-implanted jfets and laser-wafer trimming. ion-implantation permits the fabrication of precision, matched jfets on a monolithic bipolar chip. the optimizes the process to product matched bias currents which have lower initial bias currents than other popular bifet op amps. laser-wafer trimming each amplifiers input offset voltage assures tight initial match and combined with superior ic processing guarantees offset voltage tracking over the tempera- ture range. the AD642 is recommended for applications in which excellent ac and dc performance is required. the matched amplifiers provide a low-cost solution for true instrumentation amplifiers, log ratio amplifiers, and output amplifiers for four quadrant multiplying d/a converters such as the ad7541. the AD642 is available in four versions: the j, k and l, all specified over the 0 c to +70 c temperature range and one version, s, over the C55 c to +125 c extended operating temperature range. all devices are packaged in the hermetically- sealed, to-99 metal can or available in chip form. product highlights 1. the AD642 has tight matching specifications to ensure high performance, eliminating the need to match individual devices. 2. analog devices, unlike some manufacturers, specifies each device for the maximum bias current at either input in the warmed-up condition, thus assuring the user that the AD642 will meet its published specifications in actual use. 3. laser-wafer-trimming reduces offset voltage to as low as 0.5 mv max and matched side to side to 0.25 mv (AD642l), thus eliminating the need for external nulling. 4. low voltage noise (2 m v, p-p), and high open loop gain enhance the AD642s performance as a precision op amp. 5. the standard dual amplifier pin out allows the AD642 to replace lower performance duals without redesign. 6. the AD642 is available in chip form. features matched offset voltage matched offset voltage over temperature matched bias current crosstalk: C124 db @ 1 khz low bias current: 35 pa max warmed up low offset voltage: 500 m v max low input voltage noise: 2 m v p-p high open loop gain low quiescent current: 2.8 ma max low total harmonic distortion standard dual amplifier pin out available in hermetic metal can package and chip form mil-std-883b processing available single version available: ad542
AD642Cspecifications AD642j AD642k AD642l AD642s model min typ max min typ max min typ max min typ max unit open loop gain v o = 10 v, r l 3 2 k w 100,000 250,000 250,000 250,000 v/v t min to t max , r l = 2 k w 100,000 250,000 250,000 100,000 v/v output characteristics voltage @ r l = 2 k w , t min to t max 10 12 10 12 10 12 10 12 v voltage @ r l = 10 k w , t min to t max 12 13 12 13 12 13 12 13 v short circuit current 25 25 25 25 ma frequency response unity gain small signal 1.0 1.0 1.0 1.0 mhz full power response 50 50 50 50 khz slew rate, unity gain 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 v/ m s input offset voltage 1 initial offset 2.0 1.0 0.5 1.0 mv input offset voltage t min to t max 3.5 2.0 1.0 3.5 mv input offset voltage vs. supply, t min to t max 200 100 100 100 m v/v input bias current 2 either input 10 75 10 35 10 35 10 35 pa offset current 5 2 2 2 matching characteristics 3 input offset voltage 1.0 0.5 0.25 0.5 mv input offset voltage t min to t max 3.5 2.0 1.0 3.5 mv input bias current 35 25 25 35 pa crosstalk C124 C124 C124 C124 db input impedance differential 10 12 i 610 12 i 610 12 i 610 12 i 6m w i pf common mode 10 12 i 610 12 i 610 12 i 610 12 i 6m w i pf input voltage range differential 4 20 20 20 20 v common mode 10 12 10 12 10 12 10 12 v common-mode rejection 76 80 80 80 db input noise voltage 0.1 hz to 10 hz 2 2 2 2 m v p-p f = 10 hz 70 70 70 70 nv/ ? hz f = 100 hz 45 45 45 45 nv/ ? hz f = 1 khz 30 30 30 30 nv/ ? hz f = 10 khz 25 25 25 25 nv/ ? hz power supply rated performance 15 15 15 15 v operating 5 18 5 15 5 15 5 15 v quiescent current 2.8 2.8 2.8 2.8 ma transistor count 58 58 58 58 package option to-99 style (h-08b) AD642jh AD642kh AD642lh AD642sh notes 1 input offset voltage specifications are guaranteed after 5 minutes of operation at t a = +25 c. 2 bias current specifications are guaranteed at maximum at either input after 5 minutes of operation at t a = +25 c. for higher temperatures, the current doublers every 10 c. 3 matching is defined as ther difference between parameters of the two amplifiers. 4 defined as the maximum safe voltage between inputs, such that neither exceeds 10 v from ground. specifications subject to change without notice. specifications shown in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. rev. 0 C2C outline dimensions dimensions shown in inches and (mm). to-99 45 bsc 0.100 (2.54) bsc 0.034 (0.86) 0.027 (0.69) 0.045 (1.14) 0.027 (0.69) 0.160 (4.06) 0.110 (2.79) 0.100 (2.54) bsc 0.200 (5.08) bsc 6 8 5 7 1 4 2 3 reference plane base & seating plane 0.335 (8.51) 0.305 (7.75) 0.370 (9.40) 0.335 (8.51) 0.750 (19.05) 0.500 (12.70) 0.045 (1.14) 0.010 (0.25) 0.050 (1.27) max 0.040 (1.02) max 0.019 (0.48) 0.016 (0.41) 0.021 (0.53) 0.016 (0.41) 0.185 (4.70) 0.165 (4.19) 0.250 (6.35) min (@ + 25 c, and v s = 15 v dc) metalization photographic contact factory for latest dimensions. dimensions shown in inches and (mm).
AD642 rev. 0 C3C figure 7. input bias current vs. cmv figure 10. open loop frequency response figure 2. output voltage swing vs. supply voltage figure 5. input bias current vs. power supply voltage figure 8. change in offset vs. warm-up time figure 11. open loop voltage gain vs. supply voltage figure 12. power supply rejection vs. frequency figure 9. open loop vs. temperature figure 6. input bias current vs. temperature figure 3. output voltage swing vs. load resistance figure 1. input voltage range vs. supply voltage figure 4. quiescent current vs. supply voltage typical characteristicsCAD642 rev. 0 C3C
AD642 rev. 0 C4C figure 15. output swing and error vs. output settling time (circuit of figure 23) figure 13. common-mode rejection ratio vs. frequency figure 16. total harmonic distortion vs. frequency figure 14. large signal frequency response figure 17. input noise voltage spectral density figure 19. t. h. d. test circuits figure 20. crosstalk test circuit figure 21a. unity gain follower pulse response (large signal) figure 21b. unity gain follower pulse response (small signal) figure 21c. unity gain follower 2 m s 5v 1 m s 50mv figure 22a. unity gain inverter figure 22c. unity gain inverter pulse response (small signal) 1 m s 50mv figure 22b. unity gain inverter pulse response (large signal) 2 m s 5v a. unity gain follower b. follower with gain = 10 figure 18. total noise vs. source impedance
AD642 rev. 0 C5C figure 23. settling time test circuit fast settling time (8 m s to 0.01% for 20 v p-p step), low power and low offset voltage make the AD642 an excellent choice for use as an output amplifier for current output d/a converters such as the ad7541. 1mv 5 m s 10v v error 1mv/div input 10v/div figure 24. settling characteristic detail the upper trace of the oscilloscope photograph of figure 24 shows the settling characteristic of the AD642. the lower trace represents the input to figure 23. the AD642 has been designed for fast settling to 0.01%, however, feedback compo- nents, circuit layout and circuit design must be carefully considered to obtain optimum settling time. figure 25. 0.1 hz to 10 hz 2nd order bandpass filter, maximally flat the low frequency (1/f) noise has a power spectrum that is inversely proportional to frequency. typically this noise is not important above 10 hz, but it can be important for low fre- quency-high gain applications. the low noise characteristic of the AD642 make it ideal for 1/f noise testing circuits. the circuit of figure 25 is a 0.1 hz to 10 hz bandpass filter with second order filter characteristics. the circuit illustrated in figure 26 uses two AD642s to construct an instrumentation amplifier with low input current (35 pa max), high linearity and low offset voltage and offset voltage drift. the ad644 may be substituted for increased speed, but the higher open-loop gain of the AD642 maintains better linearity over the gain range of 1 to 1000. amplifier a1 is an AD642l for low input offset voltage (250 m v max) and low input offset voltage drift at high gains because matching and tracking are very important for the balanced input stage. amplifier a2 serves two nonrelated functions, output amplifier and active data-guard drive, and does not require close match- ing between sections; thus it may be an AD642j. figure 26. precision fet input instrumentation amplifier the output impedance of a cmos dac varies with the digital word thus changing the noise of the amplifier circuit. this effect will cause a nonlinearity whose magnitude is dependent on the offset voltage of the amplifier. the AD642k with trimmed offset will minimize the effect. the schottky protection diodes recommended for use with many older cmos dacs are not required when using the AD642. figure 27a. AD642 used as dac output amplifier figure 27a illustrates the ad7541 12-bit digital-to-analog converter, connected for bipolar operation. since the digital input can accept bipolar numbers and v ref can accept a bipolar analog input, the circuit can perform a 4-quadrant multiplication. v ref in, 20v p-p, 33khz 10v/div vert, 5 s/div horiz. settling time: 10 s to 0.01% on 20v step 10v 5? 5v v out 5v/div vert, 5 s/div horiz. figure 27b. voltage output dac settling characteristic the photo above shows the output of the circuit figure 27a. the upper trace represents the reference input, and the bottom trace shows the output voltage for a digital input of all ones on the dac. the 47 pf capacitor across the feedback resistor compensates for the dac output capacitance, and the 150 pf load capacitor serves to minimize output glitches. log amplifiers or log ratio amplifiers are useful in applica- tions requiring compression of wide-range analog input data,
AD642 rev. 0 C6C AD642 linearization of transducers having exponential outputs, and analog computing, ranging from simple translation of natural relationships in log form (e.g., computing absorbance as the log- ratio of input currents), to the use of logarithms in facilitating analog computation of terms involving arbitrary exponents and multiterm products and ratios. the picoamp level input current and low offset voltage of the AD642 make it suitable for wide dynamic range log amplifiers. figure 28 is a schematic of a log ratio circuit employing the AD642 that can achieve less than 1% conformance error over 5 decades of current input, 1 na to 100 m a. for voltage inputs, the dynamic range is typically 50 mv to 10 v for 1% error limited on the low end by the amplifiers input offset voltage. figure 28. log-ratio amplifier the conversion between current (or voltage) input and log output is accomplished by the base emitter junctions of the dual transistor q1. assuming q1 has b> 100, which is the case for the specified transistor, the base-emitter voltage on side 1 is to a close approximation: v be a = kt / q ln i 1 / i s 1 this circuit is arranged to take the difference of the v be s of q1a and q1b, thus producing an output voltage proportional to the log of the ratio of the inputs: v out = k ( v be a v be b ) = kkt q (ln i 1 / i s 1 ln i 2 / i s 2 ) v out = kkt / q ln i 1 / i 2 the scaling constant, k is set by r1 and r tc to about 16, to produce 1 v change in output voltage per decade difference in input signals. r tc is a special resistor with a +3500 ppm/ c temperature coefficient, which makes k inversely proportional to temperature, compensating for the t in kt/q. the log-ratio transfer characteristic is therefore independent of temperature. this particular log ratio circuit is free from the dynamic prob- lems that plague many other log circuits. the C3 db bandwidth is 50 khz over the top 3 decades, 100 na to 100 m a, and decreases smoothly at lower input levels. this circuit needs no additional frequency compensation for stable operation from input current sources, such as photodiodes, that may have 100 pf of shunt capacitance. for larger input capacitances a 20 pf integration capacitor around each amplifier will provide a smoother frequency response. the log ratio amplifier can be readily adjusted for optimum accuracy by following this simple procedure. first, apply v1 = v2 = C10.00 v and adjust balance for v out = 0.00 v. next apply v1 = C10.00 v, v2 = C1.00 v and adjust gain for v out = +1.00 v. repeat this procedure until gain and balance readings are within 2 mv of ideal values. the low input bias current (35 pa) and low noise characteristics of the AD642 make it suitable for electrometer applications such as photo diode preamplifiers and picoampere current-to- voltage converters. the use of guarding techniques in printed circuit board layout and construction is critical in printed circuit board layout and construction is critical for achieving the ultimate in low leakage performance that the AD642 can deliver. the input guarding scheme shown in figure 29 will minimize leakage as much as possible; the guard ring should be applied to both sides of the board. the guard ring is connected to a low impedance potential at the same level as the inputs. high impedance signal lines should not be extended for any unnecessary length on a printed circuit; to minimize noise and leakage, they must be carried in rigid shielded cables. figure 29. board layout for guarding inputs input protection the AD642 is guaranteed for a maximum safe input potential equal to the power supply potential. the input stage design also allows differential input voltages of up to 0.5 volts while maintaining the full differential input resistance of 10 12 w . this makes the AD642 suitable for low speed voltage comparators directly connected to a high impedance source. many instrumentation situations, such as flame detectors in gas chromatographs, involve measurement of low level currents from high-voltage sources. in such applications, a sensor fault condition may apply a very high potential to the input of the current-to-voltage converting amplifier. this possibility necessi- tates some form of input protection. many electrometer type devices, especially cmos designs, can require elaborate zener protection schemes which often compromise overall perfor- mance. the AD642 requires input protection only if the source is not current limited, and as such is similar to many jfet- input designs. the failure mode would be overheating from excess current rather than voltage breakdown. if the source is not current-limited, all that is required is a resistor in series with the affected input terminal so that the maximum overload current is 1.0 ma (for example, 100 k w for a 100 volt overload). this simple scheme will cause no significant reduction in performance and give complete overload protection. figure 30 shows proper connections. figure 30. AD642 input protection c632cC5C12/86 printed in u.s.a.
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